1. Field of the Invention
This invention relates to a method of testing the electrical conductivity of a connection between an integrated circuit device and a circuit board to which the device is connected.
2. Description of the Related Art
A known method of testing such a connection comprises the application of potentials to circuit nodes of the circuit board and the monitoring of the responses of the circuit to these potentials. The potentials are generated by an automatic test equipment (ATE) central control system and applied to the circuit nodes by an in-circuit test (ICT) fixture of the equipment which supports the circuit board. The fixture comprises a so called bed of nails which contact the circuit nodes. The responses of the circuit picked-up by the bed of nails are passed to the central control system. The control system has full knowledge of the circuit board and the devices connected thereto and therefore knows what responses to expect to various patterns of potentials it generates. The control system is thus able to detect any bad connections between the devices and the board.
A disadvantage with this method is that it requires a detailed knowledge of the board and the devices connected thereto. The relevant information may not be available. Another disadvantage with this method is the lengthy time it takes to write the test program run by the central control system, which program defines the various patterns of potentials to be applied and the responses to be expected thereto.
Another known method uses the ATE system and ICT fixture mentioned above to test for the presence of a diode of the device under test connected between the pin under test and a ground supply pin of the device. The diode is part of voltage protection circuitry of the device provided for the pin under test. A voltage is applied to the pin under test to forward bias the diode, and the voltage between the pin under test and ground, i.e. the voltage dropped across the diode, is measured by the ATE system. If the characteristic forward voltage drop is measured the pin connection under test is good.
A disadvantage with this method is seen in the case where a pin of another device, similarly protected by means of a diode as the diode of the device under test, is on the same circuit node as the pin under test. If the connection of the pin under test is bad but the connection of the pin of the other device is good, the characteristic forward voltage drop will still be measured, and therefore the bad connection of the pin under test not detected.